p2.

and

	A0 ----+
               |
               +---- C0
               |
	B0 ----+

	
	A1 ----+
	       |
               +---- C1
               |
	B1 ----+


	A2 ----+
	       |
               +---- C2
               |
	B2 ----+


	A3 ----+
	       |
               +---- C3
               |
	B3 ----+


	A4 ----+
	       |
               +---- C4
               |
	B4 ----+


	A5 ----+
	       |
               +---- C5
               |
	B5 ----+


	A6 ----+
	       |
               +---- C6
               |
	B6 ----+


	A7 ----+
	       |
               +---- C7
               |
	B7 ----+




assuming input is from other logic stages or registers

exact duplicated stages



any low input -> low output,

	all inputs high -> high output (and)

